IBM, Chartered, Infineon and Samsung have developed the first commercially available design kits for low-power 45-nanometer chips, signaling that after much speculation the race has finally begun toward the next process node.

What that means in real market advantage versus technology bragging rights remains to be seen. New processes are extremely costly, even with design kits, and recouping non-recurring engineering expenses requires a larger number of chips to be sold at each new process node. Still, getting to market first with low-power chips at 45nm could offer significant cost savings to early adopters in highly competitive commercial markets such as cell phones and memory chips.

Pushing to the next node also offers significant performance gains. Exact numbers vary greatly, but Subu Iyer, director of 45nm and eTechnologies at IBM, said performance can be increased an average of 30 percent at 45 nanometers. He also said there is significant headroom for tweaking performance at low power with strain engineering.

“Strain improves ‘on current,’ We are constrained by ‘off current.’ But we still have a variety of stress techniques available to us to get more performance,” said Iyer, noting that the big question is how much the market is willing to pay for that additional performance and low power. “We are still not at the limit where we apply strain. But at some point, strain will cost more.”

There are other options for tweaking power and performance, as well. Kevin Meyer, VP of worldwide alliances and platform marketing at Chartered, said there are device-level changes that can be made to cut power and improve performance. But Meyer noted that chip performance gains are no longer the most important factor. “With low-power implementations, performance is not the highest measure of success. At 45, what we are doing is controlling leakage through strain. That’s a key driver for certain markets like cell phones.”

It’s also a key reason that Samsung and Infineon have jumped into the alliance with IBM and Chartered. “For us, performance, low power and chip cost are all important,” said Walter Neumueller, senior director of technology alliances at Infineon. “This is about using low standby power for wireless and communications.”

The first working circuits in 45nm technology were proven in silicon at IBM’s fab in East Fishkill, N.Y, which is where the joint development team is based, with the process expected to be installed and qualified at Chartered, Samsung and IBM by the end of next year. Among the blocks verified so far are standard library cells and I/O. In addition, all four companies contributed to the design kits, which are aimed at speeding development and increasing interest for the new process node.